Abstract
This talk introduces ASPO, an approach that leverages disjunctive form to enable Bayesian Optimisation (BO) to handle constraints involving categorical parameters. ASPO supports categorical parameters using a novel customized BO covariance kernel. It also accelerates the design evaluation procedure by penalizing the BO acquisition function with potential evaluation time and by reusing FPGA synthesis checkpoints from previously evaluated configurations. ASPO targets three soft processors: RocketChip, BOOM, and EL2 VeeR, and is evaluated based on seven RISC-V benchmarks.
Biography
Wayne Luk is Professor of Computer Engineering at Imperial College London, and the head of the Custom Computing Research Group there. His research focuses on foundation and applications of hardware acceleration, reconfigurable systems, and design automation. He co-founded ACM Transactions on Reconfigurable Technology and Systems (TRETS) and was the first Editor-in-Chief. He is a Fellow of the Royal Academy of Engineering, a Fellow of the IEEE, and a Fellow of the BCS.
(This is one of the research talks delivered at Next Generation EDA Workshop, organised by CEDAR on 26 October 2026.)
