Innovating EDA Solutions
Transforming Electronic Design Automation with AI
CEDAR advances Electronic Design Automation through cutting-edge AI, large circuit models, and high-performance computing, paving the way for the next generation of semiconductor technology.
The Centre for Next Generation EDA Research in Hong Kong
CEDAR is a leading research and innovation centre located in Hong Kong dedicated to revolutionizing Electronic Design Automation (EDA). We collaborate with top academics and industry leaders to develop innovative solutions for integrated circuits and heterogeneous systems.
At CEDAR, we specialize in leveraging artificial intelligence and advanced computing to create transformative technologies for chiplets and integrated circuits. Our commitment to excellence has garnered multiple awards and recognitions in the semiconductor innovation landscape.
Driven by a mission to support Hong Kong’s semiconductor vision, CEDAR excels in crafting next-generation EDA tools and technologies.
TEAM MEMBERS
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INVESTMENT (HKD)
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PAPER PUBLISHED
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DESIGN REPOSITORIES
What Sets Us Apart
#1 in the World for EDA Research
Led by CUHK, ranked World No. 1 in Electronic Design Automation (EDA) by CSRankings, CEDAR builds on a world-leading foundation of research excellence, innovation, and impact in semiconductor design automation.
HK$75 Million Research Initiative
A five-year flagship programme dedicated to transforming chip design through AI-powered automation and advanced computing technologies.
Global Research Partnership
Uniting experts from four leading Hong Kong universities, international collaborators, and major semiconductor companies including MediaTek and ASE.
Key Innovations
Large Circuit Models (LCMs)
The first step toward “foundation models” for chip design, enabling AI to understand circuits across every stage of development.
AI-Native EDA
Moving beyond traditional automation by embedding AI directly into the chip design process, from optimization to verification.
100x Faster Design Possibilities
Leveraging GPU and many-core CPU technologies to dramatically reduce design turnaround times and unlock new levels of design quality. The proposal targets massive parallelism across the entire RTL-to-GDS flow.